Miniaturization of a semiconductor pattern has been approaching its limit. Accordingly, there have been suggestions for a large number of three-dimensional layouts in which storage elements are not only arranged in a conventional XY plane but also arranged in a Z axis direction. As the storage elements, a ferroelectric random access memory (FeRAM), a magnetoresistive random access memory (MRAM), a phase change random access memory (PRAM), a resistance random access memory (ReRAM), and an organic memory have been devised.
As an example of a method of producing the three-dimensional layout, layers of combinations each comprising a storage element held between an upper electrode and a lower electrode are stacked in the Z axis direction, and n×m storage elements are arranged in the XY plane. Adjacent elements are insulated from each other by embedding an insulating film therebetween. A method to produce a device having such a layout is taken for instance. According to this method, a first storage element and upper and lower electrodes are processed by an L/S pattern, and an insulating film is embedded in spaces. A second L/S pattern is then processed at right angles with the L/S pattern lying immediately under the second L/S pattern, and an insulating film is embedded again.
For the insulating film, it is possible to use silicon dioxide formed by, for example, a chemical vapor deposition (CVD) or a coating method, or a carbon-containing silicon compound which is produced by bonding its organic matter to polysiloxane or silsesquioxane produced by a coating method. These materials are also used as low-k materials, and organic matter such as SILK™ may also be used. Another way used to produce silicon dioxide is to oxidize polysilazane having an Si—N bond.
However, if the number of stacked layers increases, the thickness of the insulating film in the Z axis direction increases, so that cracks are easily caused. In order to avoid this, it is preferable to embed a structurally strong filling material such as silica particulates or colloidal silica. However, when these filling materials are used, the quality of the film is not uniform. Therefore, if lithography is used to create a pattern, the border of the pattern after the processing of the insulating film becomes more uneven than when no filling material is used, so that so-called line edge roughness (hereinafter briefly referred to as “LER”) increases. When advancing miniaturization brings a wiring pattern to a nanometer size, the LER greatly could affect the features of semiconductor devices, for example, varies wiring resistance.